Design of Power, Dynamic Range, Bandwidth and Noise Scalable ADCs

The proliferation of portable electronic devices with high data-rate wireless communication capabilities and the increasing emphasis on energy efficiency is continuously applying pressure on the performance and power consumption of ADCs and other mixed-signal systems. Power scalable designs enable an ADC core to be reusable under different input and sampling frequency conditions improving system efficiency. The power consumption of pipeline and RD ADCs scales approximately linearly with sampling rate and roughly quadruples for every additional bit resolved. Hence, increasing the performance requirements of an ADC in a system can significantly increase the power consumption to impractical levels especially in a battery powered environment. The approaches presented in this chapter focus on design techniques for power scalable and low power pipeline and bandwidth scalable continuous-time RD ADCs. 2.